`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/04/07 12:15:16
// Design Name: 
// Module Name: PrGieGie
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_PrGieGie();

parameter CLK_PEERIOD = 16; // 20ns

reg         sys_clk;
reg         sys_rst_n;
reg         usb_rxf_n;
reg         usb_txe_n;
reg [7:0]   cnt;
reg [7:0]   data_cnt;

wire        usb_oe_n;
wire [7:0]  usb_data;

initial begin
    sys_clk = 1'b0;
    sys_rst_n = 1'b0;
    usb_txe_n = 1'b0;
    usb_rxf_n = 1'b1;
    cnt = 8'd0;
    #200
    sys_rst_n = 1'b1;
end

always #(CLK_PEERIOD / 2) sys_clk = ~sys_clk;

always @(negedge sys_clk) begin
    if ((cnt < 8'd255) && sys_rst_n)
        cnt <= cnt + 8'd1;
    else
        cnt <= cnt;
end

always @ (negedge sys_clk) begin
    if ((cnt < 8'd255) && sys_rst_n)
        usb_rxf_n = 1'b0;
    else
        usb_rxf_n = 1'b1;
end

always @(posedge sys_clk) begin
    if ((!usb_oe_n) && (!usb_rxf_n))
        data_cnt <= data_cnt + 8'd1;
    else
        data_cnt <= 8'd0;
end

assign usb_data = (!usb_oe_n) ? data_cnt : 8'hzz;

PrjGieGie u_prjGieGie(
    .usb_clk_60m    (sys_clk),
    .rst_n          (sys_rst_n),
    .usb_rxf_n      (usb_rxf_n),
    .usb_txe_n      (usb_txe_n),
    .usb_oe_n       (usb_oe_n),
    .usb_rd_n       (),
    .usb_wr_n       (),
    .usb_siwu_n     (),
    .usb_data       (usb_data)
    );

endmodule
